1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to methods and apparatus for low power memory accessing techniques.
2. Description of the Related Art
Semiconductor memory cores are usually laid-out in array format, such that each individual core cell is coupled by a wordline and a pair of differential bitlines. To access data stored in a selected core cell, associated memory accessing circuitry is commonly designed around a memory core. For example, some of the key memory accessing circuitry typically includes addressing circuitry for selecting a core cell, wordline drivers for driving a selected wordline, and sense amplifiers for amplifying the signal read from the selected core cell.
In low power memory applications, there is typically a need to reduce the amount of power consumption that occurs at every stage of a memory's function. Conventionally, memory designers have been using a bank architecture to reduce power consumption, when access to particular columns in a memory core are performed. In general, a bank architecture will generally include a plurality of banks that are used to individually address a single core cell (i.e., one for each bit) along a selected wordline.
This is contrary to other conventional memory accessing circuitry, such as bit sliced architectures that use Y-MUX decoders to access "m" columns of a memory core. As is well known, when a Y-MUX decoder accesses a particular core cell, all other core cells that lie along the selected wordline will also be accessed, and therefore consume power. As such, in low power applications, designers prefer to use bank architectures as compared to bit sliced architectures, to reduce the amount of power being consumed during memory access operations.
As mentioned above, the bank architecture is superior to the bit sliced architectures in terms of power consumption, because only one column per bit in a memory core will be accessed by a bank at one time, and thereby eliminates the power consumed by non-selected columns. For ease of understanding, FIG. 1 shows a conventional bank architecture for performing write operations to a memory core. As shown, an input write circuit 102 is provided to receive data from a user, and then output a differential signal (i.e., global data bus "GDB", "/GDB"), that is transferred to a BANK 1.
In most prior art systems, the input write circuit 102 is configured to output the differential signals GDB and /GDB to each of the banks that may be used to access the number of columns contained in a particular memory device. As pictorially illustrated, the input write circuit 102 is generally configured to drive any number of banks up to BANK N, when a memory core has N columns per bit. Therefore, when BANK 1 is selected to write data to a core cell 110, a BANK 1 select signal will be passed to a bank interface circuit 104. Bank interface circuit 104 is then configured to output a differential signal (i.e., BIT, and /BIT) to the core cell 110 when a wordline 112 is selected.
A problem with the bank architecture 100 of FIG. 1 is that a substantial amount of power is consumed during writing operations. For example, the data that is being written to the core cell 110 is being fed through the input write circuit 102, and through a large global data bus (GDB, /GDB) that is driven at full rail voltages. For example, the logical elements in this circuitry are driven by signals that swing between Vss and Vdd (e.g., 0 and 2.5 volts). As such, the power consumed in performing the write operation is many times too large for applications that require substantially lower power consumption.
By way of example, the power consumed through a particular circuit is measured by the equation, Power=CV.sup.2 f. Therefore, a major component of power is the voltage level that is used to drive the large global data bus in a banking architecture. In this example, assuming that Vdd is equal to 2.5 volts, the frequency is 1 MHz, and the capacitance is 1 pf. The power consumption will be about 6.25 .mu.Watts. Further, the large global data bus (GDB and /GDB) generally has a very heavy capacitive load, that unfortunately translates into more power being consumed to drive the large global data bus.
In view of the foregoing, there is a need for low power bank architecture memories that implement techniques that substantially reduce the voltage swing used to drive the global data bus, and thereby substantially reduce power consumption in low power memory applications.